TY  - BOOK
AU  - Vyemura, J P
TI  - Chip design for submicron VLSI:cmos layout and simulation
SN  - 9788131501955
U1  - 621.38 
PY  - 2006///
CY  - Australia
PB  - Cengage learning
KW  - CHIP DESIGN
KW  - VLSI
ER  -