Chip design for submicron VLSI:cmos layout and simulation
Vyemura, J P
Chip design for submicron VLSI:cmos layout and simulation John P Uyemura - Australia Cengage learning 2006 - xvi, 411p.
9788131501955
CHIP DESIGN
VLSI
621.38 / UYE-C
Chip design for submicron VLSI:cmos layout and simulation John P Uyemura - Australia Cengage learning 2006 - xvi, 411p.
9788131501955
CHIP DESIGN
VLSI
621.38 / UYE-C